As technology advances, there is an increased desire to fit increasingly complex circuitry within increasingly smaller devices. As a result, the number of cores that comprise an SOC has steadily increased over time. Currently, cores are physically wired together on a silicon chip to facilitate communication between the various functions such as processors, memory, I/O, etc. With the increasing number of cores, it has become more difficult to manage the congestion of wires associated with communication between the cores on a chip. As a result, the amount of space consumed by physical wires may limit the number of cores that may be included on a chip.
In an effort to reduce the amount of space consumed by wiring between cores, some wires are bundled together to form buses for more efficient communication. However, a bus is limited by its bandwidth and architecture. Many times only one core can communicate on the bus at any given time. Although there may be more advanced architectures that allow more than one core to communicate via the bus at a time, the physical wires connecting cores are still required. Thus, the number of cores that may be included on a chip may still be limited even where advanced architectures are utilized.